Tag Archive for audio amplifier

Sony TA-F270 Inside

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I had a Sony TA-F270 over for repairs and i thought i should how you how it looks inside.

Service manual is available online if you search on Google.

Sony TA-F270 inside

Sony TA-F270 inside

Sony TA-F270 inside

Sony TA-F270 inside

Sony TA-F270 inside

A pair of power transistors were busted so i replaced them.

Sony TA-F270 inside

Here is a short video on how to do it.

Thank you for visiting

Monitoring Amplifier モニターアンプ P3: Speaker Coupling Delay

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Hello, こんにちは,


In this article i will present a simple delay circuit that will be used to couple the speakers to the amplifier after a certain settling time was allowed. The circuit also allows for to be controlled by an external 5V logic signal. This can be used to decouple the speakers in case a fault is detected.


The circuit schematic is presented in figure 1 and as you can see it uses just discrete components. It is a linear voltage ramp generator that commands a power transistor. The current charging capacitor C1 and the capacitor’s value are the parameters that set the ramp’s slope.


Speaker delay circuit schematic

Figure 1

In figure 1 Q3 forms a constant current source adjustable via POT1. R1, R2, D1, D2 set a voltage on the base of Q3 of about 5.4V and this means about 6V voltage drop over R6 and POT1 series connection. Assuming Ic3 = Ie3=Icharge,

Icharge = 6V/(R6+POT1)

Lets set POT1 at 90kohms for ease of calculation. This gives R6+POT1 = 100k.

Icharge = 60uA

Since Q3 is in saturation mode we can assume a voltage drop over C-E of about 0.5V so the voltage over the capacitor Vc1= 5.5V. The time for the capacitor to be charged to 5.5V is defined by the below equation:

T= (C1*Vc1)/Icharge = 0.91 second


Q2 buffers the voltage across C1 capacitor. It also provides a small delay until Vc1 reaches around 0.6V to bias Q2’s B-E junction. Q1 acts as a switch and when turned on via a 5V signal it absorbs most of the current from Q3 and capacitor will not be charged.

Q4 has the role to drive the relay. It is a small power transistor and it’s enabled via POT2. This variable transistor has the role to set the on/off steps based on the ramp voltage. If too low the relay will be on very fast and stay on if too high the relay will never activate.

Speaker delay circuit schematic

Figure 2

In figure 2 the time step is 200ms and we can see the ramp is about 1s long, very close to what we calculated. The blue trace is the Fault signal. When a 5V pulse is present the capacitor C1 is discharged very fast (pink trace) and speakers are decoupled (green trace). When the fault signal goes to logic low or ground the ramp generator shortly starts the process and enables the relay after about 1 second.

Speaker delay circuit schematic

Figure 3


Speaker delay circuit schematic

Figure 4

Figure 3 shows how the relay is activated faster if the POT2 is set too low in value and figure 4 shows a correct setting. The yellow trace represents power switched on.

Below you can see the circuit in the right side of the board.

Speaker delay circuit schematic スピーカ遅延回路図


Parts list does not contain the connectors in the schematic because the circuit most likely will be used as a part of something bigger:

Part Quantity
BC549 2
BC559 1
BD139 1
1N4001 3
R 12K 5% 0.25W 3
R 10K 5% 0.25W 2
C 10u 25V 1
POT 250K 1
POT 10K 1

Thank you for visiting,